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| From: Crown (all posts)
Date: 1998-09-07
Subject: Timers test result
|
Hi there,
I made some test regarding the timers in the plus4. I got some very interesting results. They are aligned as I awaited,
but all three behaves differently.
Lets see first what happens if the timer high byte write happens on an even cycle (even cycles are what the CPU can get in slow mode having
$ff1e values like $c4 $c8 etc...)
Write
is
here Timer 1 $ff $ff $fe $fe $fd $fd $fc $fc $fb $fb Timer 2 $ff $ff $ff $fe $fe $fd $fd $fc $fc $fb Timer 3 $ff $fe $fe $fd $fd $fc $fc $fb $fb $fa
e o e o e o e o e o
Now lets see when the write happened on an odd cycle (cycles the CPU can get only in fast mode)
Write
is
here Timer 1 $ff $fe $fe $fd $fd $fc $fc $fb $fb $fa Timer 2 $ff $ff $fe $fe $fd $fd $fc $fc $fb $fb Timer 3 $ff $ff $fe $fe $fd $fd $fc $fc $fb $fb
o e o e o e o e o e
So timer 1 decrementation happens on odd-even boundary, and there is no delay.
Timer 2 decrementation happens on even-odd boundary, and there is a delay if the write was on an even cycle.
Timer 3 decrementation happens also on even-odd boundary and there is no delay.
I will do some further test, as I'm curious about when they reach zero, when do they set exactly $ff09, and initiate the IRQ.
I will also test what happens when such decrements happen as
$0101->$0100->$00ff->$00fe.
$ff1e writes will not influence this, as there is no possibility to make an even cycle odd and vica versa.
Tibor Biczo / Crown of GOTU ICQ : 15989510
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