Posted By
Fuzzweed
on 2024-12-09
04:09:14
|  Can an interrupt be interrupted
What is the behaviour of handling a new interrupt?
Will a new interrupt be processed after clearing ff09 (but you may still be within the first handler) or only after RTI?
|
|
Posted By
SukkoPera
on 2024-12-09
04:47:51
| Re: Can an interrupt be interrupted
I'm no expert 6502 programmer by any means, but I think the 6502 automatically disables the interrupt flag when it jumps to the ISR, so unless you reenable it in the ISR itself, that shouldn't happen.
In theory, I think an NMI could interrupt an ISR, but there is no way to trigger an NMI in the +4 so that shouldn't be a concern unless you are trying to write something that should also work on a C64, etc.
... But maybe you should still plan for that, since even if that pin isn't even exposed on the 8501, CPU replacements using a 6502 can make it available, leading to interesting future possibilities... Action Replay on +4, anyone? 
|
|
Posted By
gerliczer
on 2024-12-09
06:07:14
| Re: Can an interrupt be interrupted
6502 is no Z80. The interrupt is not automatically disabled in an ISR. TED is not the only possible interrupt source in a Plus/4. 264 series machines have no NMI. You should read about interrupt handling a little more. I saw C64 people discussing re-entrant interrupt handlers and exact interrupt behaviour down to clock cycle level. The No More Secrets aka NMOS 6510 Unintended Opcodes booklet probably has detailed information on this topic, too.
|
|
Posted By
SukkoPera
on 2024-12-09
09:48:53
| Re: Can an interrupt be interrupted
Are you sure? This mentions explicitly that the interrupt disable flag is set automatically when an interrupt is triggered. And so does this.
|
|
Posted By
Crown
on 2024-12-09
15:08:51
| Re: Can an interrupt be interrupted
To answer the original question, second interrupt will be processed after the RTI and atfer executing one more instruction.
Unless you do a CLI in your interrupt handler routine, which enables reentrant interrupt handling.
Two separate things mixed in the discussion above: the interrupt line will remain high during interrupt processing, until all interrupt sources are cleared. Interrupt bit in the CPU status register will be set when entering interrupt handling and cleared when exiting. The interrupt bit only sets whether ISR can be initiated when the interrupt line is high or not.
|
|
Posted By
Fuzzweed
on 2024-12-10
07:34:02
| Re: Can an interrupt be interrupted
Many thanks
|
|
