Posted By
TLC
on 2023-03-21
08:19:27
|  Re: New Project: Hannes-compatible 256k RAM Expansion
@siz for me, things turn out like this,
- Code known to have been written by Csory himself ultimately always use P4=1, P5=0. (masm 256k too).
- Solder's ramregs.txt already does outline the "1 out of 4" schema for expansion logic activation. He got the particular bit combination documented wrong (...I think people are generally prone to overlook this whichever-similarly-looking-one-out-of-2 sort of choice in practice, I know I am), still, this clearly documents one thing, that is, a step made further from the "2 out of 4" (XOR gate based) activation schema. Thinking of Solder's, I certainly wouldn't have dared to invent this non-transparent modification by myself, without having reached an agreement with Csory over the matter first. (And AFAIK they're indeed known to have been sharing ideas and informations. Solder practically always detailed and documented the work previously done by Csory, Solder's SID-card has been voluntarily made compatible to Csory's, etc. etc. etc.) So I think even if, let's say, the idea of the final activation schema came from Solder rather than Csory, that definitely must have happened with Csory's knowledge and consent.
- Amongst the 256K capable setups assembled by Solder, should be at least a lot, that implement the P4=1, P5=0 activation schema. 256KB_3.PLD clearly shows that he has been actively using this, and he likely used the GAL based approach whenever possible, because, as he wrote, he specifically implemented that to reduce the amount of manual work necessary. (Agreed... by the existing Csory compatible setups once assembled by Solder, today, we're probably talking about a very small number.)
Christian probably still knows the definitive answer... 
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