Posted By
SukkoPera
on 2022-08-25
03:04:41
|  Re: Solder's SIDcard Replica
Yeah, sorry, I was adding/editing things as I found them out. I'll try to recap:
The first image in the previous post suggests that bad SID accesses always happen during double clock periods.
But the card did not always sound the same. Sometimes it would almost not sound at all. Initially I attributed this to bad contacts but then I made another capture and noticed that when this was the case, almost all the SID accesses were bad.
So I thought: maybe the initial state of the counter (i.e.: clock divider) is random and if it starts at 1 most SID accesses will be misaligned and just a few will be correct, exactly opposite to the situation I had seen before.
I had already thought of connecting the /RESET signal to the counter during PCB design but I hadn't done it because the counter wants an active-high reset. But then I noticed the GAL had a few unused pins, so I quickly made an inverter out of two, added some wires and started resetting the counter with the whole machine. This *seems* to avoid the bad case and to always put the board in the "only a few" misaligned SID accesses.
The recording was made after that, but it should basically correspond to the case shown in the first image of the previous post, where a SID read and subsequent write will result in one of them being misaligned when done during double clock periods. I haven't made another capture after the reset fix but I can do it tonight.
So something more must be required on the HW side, as I would expect any care that should be taken in SW to be already implemented in the Ninja demo (but I also tried another demo and even the SIDcard version of Lykia, they all sound the same),
Is there a way I can disable the dynamic clocking before running the demo?
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