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| From: Marko_Mäkelä
Date: 2001-07-25
Subject: Re: interrupt
|
On Wed, 25 Jul 2001, Almos Rajnai wrote:
> On 24 Jul 2001, at 15:05, Hársfalvi Levente wrote:
>
> > Yes it should do like that, as far as I'm concerned. The IRQ line
> > remains asserted as long as there's at least one pending IRQ. Now,
>
> But it means, that this code will not work:
It depends on what you mean by "working". With my interpretation of the word and of your example code, the code will work if the processor fetches an RTI (or equivalent instructions) at $0000 and at <irq. (Neither location was assigned any value in your program.)
In this case, the processor would be interrupted again right after the instruction executed after the RTI. It could be something like this:
(IRQ cannot be triggered before the CLI, since interrupts are disabled)
CLI
(IRQ cannot be triggered here, since the instruction pipeline must be emptied)
LDA #<irq
(IRQ is triggered the first time)
0000: RTI
STA $FFFE
(IRQ is triggered the second time)
<irq: RTI
LDA #>irq
(IRQ is triggered the fourth time)
<irq: RTI
STA $FFFF
(IRQ is triggered the fifth time; this time it'll work as you probably expected)
irq: ASL$FF09
RTI c: JMP c
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