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| From: Marko_Mäkelä
Date: 2001-07-24
Subject: Re: interrupt
|
On Tue, 24 Jul 2001, Almos Rajnai wrote:
> So, here come my quiestions:
>
> What does happen when an interrupt request cannot be taken?
The only interrupt source in the plus/4 is IRQ, which is a level-triggered interrupt. Whenever the IRQ signal is active (low state, 0 volts) and the I flag in the processor is clear, and the processor is about to fetch the next instruction in 2 cycles, it'll execute the IRQ sequence instead.
The NMI interrupt (not found in the plus/4) is level-sensitive: whenever the line goes from high state to low state, the processor remembers that it'll have to execute NMI after the current instruction finishes. It'll fetch yet another instruction if the NMI comes less than 2 cycles before the execution of the current instruction ends.
> Unfortunately I cannot check out on a real Plus/4, I have no
> opportunity of reaching one. (My little brother using it in an other
> city... :)
The next best thing you can do is to get the 64doc document that at least used to be distributed with VICE. I've tried to describe the BRK/IRQ/NMI logic there. Even the situation where an NMI occurs during the execution of a BRK is covered. In that case, the processor will jump to the NMI vector with the B flag set in the status register.
Marko
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