Previous | Next
| From: Richard Atkinson
Date: 2000-08-09
Subject: Re: Relative addressing
|
On Wed, 9 Aug 2000, Tim Böscke wrote:
> One reason for the high clock rate of the Z80 is the integrated DRAM
> controller.
> The Clock has to be higher than the actual memory cycle clock since each RAM
> access requires several phases.
> The 6502 does not interface its DRAMS directly and thus the help of a higher
> external clock signal is required for correct DRAM timing. You might compare
> this to the Z80 clock.
Actually, DRAM refresh cycles are very similar to read cycles, which the
6502 does perform. The Z80's DRAM refresh mechanism refreshes DRAMs *far*
more often than is actually required (compare with the VIC-II's 5
refreshes per 126 memory cycles) and is limited to a 7 bit refresh counter, which means that the Z80 can only refresh 4164, 41416 and smaller DRAMs.
Richard
--
Richard Atkinson Software Engineer Tenison Technology EDA Ltd http://www.tenisontech.com/
|
| |
Copyright © Plus/4 World Team, 2001-2024 |
