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From: Bionic (all posts)
Date: 2000-07-25
Subject: Re: Interrupts

> On Tue, 25 Jul 2000, Marko Mäkelä wrote:
>
> > Read the 64doc file advertised earlier today. :-) The first two cycles of
> > all instructions are the same: fetch from PC and PC+1.
>
> Even NOP, INX, TAX etc? They must throw away the PC+1 byte, and then read
> it on the next cycle as the PC opcode fetch.

Exactly..

This behaviour is due to the pipelining of the 6502. All instructions are decoded in cycle two after the opcode was read in cycle one. Thus the CPU does not know whether there is a second instruction byte required at the beginning of cycle two, so it starts reading byte two anyways. This is better than reading nothing in cycle two, since otherwhise two byte instructions would take at least three cycles.

With a more complex control logic it would be possible to avoid the fetching of bogus operand bytes in the second cycle, but chip space was expensive back then ..