| Posted By
seff
on 2021-02-01
15:25:40
 |  Bus timing diagram for 264 family computers
I am studying the TED cycles and its modus operandi.
The cycles are briefly described in
SVS-UltimateMap_v2-1.xls hardware sheet:
Can somebody explain to us mortals the following (rows 7-12)?
Bus access in fast mode DMA (22+3) - I assume this is the bad line (TED fetches 40 bytes into its internal memory)
Bus access in slow mode DMA (14+3)
Bus access in fast mode normal (65) - I assume this is the window area + left/right borders
Bus access in slow mode normal (57)
Bus access in fast mode border (109) - I assume this is the upper/lower border line (or blank screen enabled)
Bus access in slow mode border (57)
What is the difference between the fast mode and the slow mode?
I would appreciate if you could explain the principles to me in a simple way, I am happy to update SVS-UltimateMap for future reference.
Thanks!
PS:
I am trying to understand the subject from various posts:
forum/39056/-/badline
forum/36905
forum/39027#39056
plus4encyclopedia/500027
plus4encyclopedia/500152
kb.php?id=500024
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Posted By
unclouded
on 2021-02-04
20:55:21
| Re: Bus timing diagram for 264 family computers
I don't know, so I hope someone else will chime in, but it could perhaps be something to do with operating in 2 MHz or 1 MHz mode (Bit 1 of $FF13), or whether the TED permits the CPU (AEC, RDY?) access to the bus when PHI2 is low or whether it uses both halves of the cycle to load graphics data (so much to load at this time!) thus "stunning" the CPU and making fewer cycles available for logic at that time.
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Posted By
seff
on 2021-02-05
01:30:06
| Re: Bus timing diagram for 264 family computers
Yes, that's right, looking at the table, the second phase (PHI2) is never occupied by the CPU.
I think it is depicted on Figure 2, I/O Control (57), possibly ZOUT?
https://patents.google.com/patent/US4569019
https://patents.justia.com/inventor/david-w-diorio
The other thing that puzzles me are the two bad lines. The TED has to fetch all information for both character and color on each line (even on the first line). But it needs two lines to "store" 2 x 40 bytes into its internal memory. It practically caches both character and color for the next 6 lines. Why can't this be achieved on the first line in the first place? It looks like that the "store operation" is too slow...
David W. DiOrio R.I.P.
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Posted By
gerliczer
on 2021-02-05
03:18:26
| Re: Bus timing diagram for 264 family computers
Hey seff,
Do you happen to know Bo Zimmerman's excellent Commodore Archive? Fascinating things are there.
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