Posted By
IstvanV
on 2008-02-08
11:33:52
|  Re: plus4emu 1.2.5.1
It is because the CPU has three cycles before the DMA when it is allowed to write, but not to read (or, more precisely, the read does take place, but the result is discarded and the read cycle is repeated). The count of three cycles is because the largest number of write cycles in a row is three, and it happens when the PC and the status register are saved on the stack on an interrupt. Read-modify-write instructions like INC, DEC, etc. have two write cycles at the end, the first one just writes back the original value, and the second writes the correct result. Simple write instructions like STA have one write cycle at the end. So, with the proper timing, it is possible to get one or two write cycles to occur in the three special pre-DMA cycles, thus getting more than 22 cycles in a single line. Normally, these cycles are the ones when reading from FF1E would return CE, D2, or D6. In the following example, if the 'sty $FF16's were replaced with 'ldy $FF1E', they should return C2:
ldy #$??
sty $FF16
sta $FF14
ldy #$??
sty $FF07
ldy #$??
sty $FF15
ldy #$??
sty $FF16
stx $FF1D
ldy #$??
sty $FF07
ldy #$??
sty $FF15
ldy #$??
sty $FF16
inc $FF14
...
A useful reference on 6502 timing and other details is this document: http://www.viceteam.org/plain/64doc.txt
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