Posted By
MasK
on 2007-02-08
16:35:22
|  Re: Plus/4 Expansion port...
Sorry about the "guess" joke 
The second (DMA based?) mechanism isn't clear for me...my idea wasn't correct,I can see it now...
But maybe we have to "back to roots",and think again everything...
Thanks to TLC summarizing all cases...there must be a simple way,to do this!!
""(E.g. the next CPU read cycle after a single CPU write cycle is predictably an opcode fetch of the next instruction).""
I think,this is our point..not too hard to find out,if only single write happen,and a read is coming now....this is the moment,when we need to pull data bus low.
Interrupts+dma are can't affect this..every code must use some simple memory writing instuctions.
If we don't missing something,this is the perfect freezer solution,only we need now a better monitor and some additional code for freezer's functions.
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