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Posted By

TLC
on 2007-02-08
06:33:11
 Re: Plus/4 Expansion port...

First I though, you must be my old friend BSZ/NST (deducting from the enthusiastic attitude and the fact that he's rarely (if ever) seen here amongst those that can get the principle of this hack at all happy )... Well, this method, unfortunately, won't work. The description would be true for interrupts, but not for DMAs. When the CPU is interrupted, the currently executed instruction is finished before the interrupt mechanism would be started (just like you described). For DMA requests (BA is pulled), this doesn't apply. The CPU would finish pending _write_ cycles (if there are any), and then stopped right on the next read cycle. The TED leaves 3 cycles for the CPU to finish executing consecutive write cycles. This is the "worst case" for 65xx series CPUs. (Some opcodes write just a single byte, read-modify-write opcodes + JSR write two in a row, the interrupt mechanism including the execution of BRK writes three). So, after the DMA had finished, the next memory fetch could be either opcode or operand fetch, but it's not predictable.

(Your idea could work in some cases "accidentally", BTW. The reason is, most opcodes execute a write as the opcode's last cycle... so, in the very first cycle after a DMA, it's more likely that a memory fetch is an opcode fetch than otherwise... but not much more).



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