Posted By
Spektro
on 2024-08-17
12:24:32
 |  Time delay
What is the easiest way to wait for 1-10 seconds or longer using assembly language?
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Posted By
Lavina
on 2024-08-17
12:16:51
 | Re: Time delay
I guess I'd increment some zero page addresses: in every RI cycle you INC $D0 and you also LDA it, and if it's a given value then you increment $D1 and also load and observe that one and if it's reaches a certain value then you're done. Values depend on how much you wanna "wait", obviously. Makes sense?
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Posted By
gerliczer
on 2024-08-17
12:20:55
| Re: Time delay
IDK what is the easiest way. However, if you have KERNAL timekeeping, you can use that, if you don't, count raster interrupts once per screen refresh.
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Posted By
Spektro
on 2024-08-18
08:17:25
| Re: Time delay
I want to avoid writing an interrupt routine. With easiest I mean the shortest routine.
There seems to be a real time clock counter at memory addresses $a3-$a5. If I set them to 0 and poll $a4, I get about 4 seconds delay when $a4 is 1, about 8 seconds delay when it's 2, and so on.
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Posted By
Luca
on 2024-08-17
15:10:18
 | Re: Time delay
When Csabo suggested to me about including a countdown timed autoboot in Tomcat +GD, I used the zp way cited by you.
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Posted By
Spektro
on 2024-08-18
06:37:27
| Re: Time delay
OK, thanks Luca. I'll settle for polling those zero page addresses.
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Posted By
gerliczer
on 2024-08-18
09:16:33
| Re: Time delay
It came to my mind that as KERNAL time is 1/60th of a second based, dividing its value by 64, which is two to the power of six, will result in a fairly good approximation of a second. Therefore, checking the topmost two bits of the low byte and the value of the middle byte should give you reasonable accuracy. And it may be even simplified in your case by shifting those two bits into the middle byte and checking only that. I think it maybe worth a try.
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Posted By
Harry Potter
on 2024-08-18
09:20:51
| Re: Time delay
Why not compare the first byte to the number of jiffies you desire then trigger the routine and reset the value to 0?
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Posted By
orac81
on 2024-08-22
08:21:41
| Re: Time delay
Ok here's a simple approach
TIMER:
LDX #10. ; # seconds
T1:
LDA $A5. ; JIFFY LOW
CLC
ADC # 60
T2:
CMP $A5
BNE T2
DEX
BNE T1
RTS
untested, just of the top of my head...
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Posted By
orac81
on 2024-08-22
08:21:43
| Re: Time delay
Ok here's a simple approach
TIMER:
LDX #10. ; # seconds
T1:
LDA $A5. ; JIFFY LOW
CLC
ADC # 60
T2:
CMP $A5
BNE T2
DEX
BNE T1
RTS
untested, just of the top of my head...
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Posted By
orac81
on 2024-08-22
08:36:29
| Re: Time delay
Sorry hit post twice (but it should not double post!)
Also fscking autocorrect added full stops, ignore them. You could remove LDX #10. and the CLC, then
LDX # nsecs ; no of seconds here
JSR TIMER
For any delay upto 255 secs..
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Posted By
orac81
on 2024-08-22
08:37:52
| Re: Time delay
Sorry hit post twice (but it should not double post!)
Also fscking autocorrect added full stops, ignore them. You could remove LDX #10. and the CLC, then
LDX # nsecs ; no of seconds here
JSR TIMER
For any delay upto 255 secs..
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Posted By
retroscener
on 2024-08-22
09:10:07
 | Re: Time delay
This accidental double posting has happened to me recently too.
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Posted By
Charles
on 2024-08-22
17:45:26
| Re: Time delay
I would wait for new screen (checking $ff1c) X times you need:
ldx #$fa ;waiting 5 sec
PAUSE1:
lda #$01
PAUSE2:
bit $ff1c
bne PAUSE2
PAUSE3:
bit $ff1c
beq PAUSE3 ;waiting for new frame
dex
bne PAUSE1
On PAL screen, you need 50 frames/sec, so for more than 5 secs you need to nest another cycle with Y
@orac81, what increments ZP $A5 (jiffy clock)? I've never used that. I assume it is the standard ROM (raster) IRQ routine, is not it?
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Posted By
Spektro
on 2024-08-23
02:50:02
| Re: Time delay
First I got the impression, from the SVS-UltimateMap, that $a5 contains elapsed hours, $a4 minutes, and $a3 seconds/jiffies/something. I was puzzled why I got about a 4 seconds delay by polling the $a4.
$a3-$a5 being a 24 bit counter that is increased by 1 by the Kernal's interrupt routine makes much more sense 
I tried orac81's routine and it works perfectly. Thanks orac81!
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Posted By
orac81
on 2024-08-24
05:09:40
| Re: Time delay
You are welcome! Yes the jiffy clock is a 24 bit counter, but oddly "backwards" from a 6502 pov, ie hi byte first. it's been that way since pet 1.0 ROM.
you can save a byte in that routine, since the carry is always set after first iteration, remove CLC and use ADC # 59..
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