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From: Bionic (all posts)
Date: 2000-08-09
Subject: Re: Relative addressing

> On Wed, 9 Aug 2000, Marko Mäkelä wrote:
>
> > No, it's actually in the 5th cycle, while fetching the next opcode
(which
> > will not be thrown away, as the branch is not taken). This is the idea
> > the 6502 designers have of pipelining. This also partially explains why
> > the 6502 requires much less cycles per instruction than e.g. the Z80.
>
> Not really; the Z80 is micro-coded, whereas the 6502 is hard-wired. There

Well the difference isnt that big in this case. Basically the usage of a two level gate array reduced the 6502 core size. If the 6502 had more
(and more complex) instructions a ROM might have been a better choice.

I really wonder why people still make a fuzz about microcoded vs. hardwired
?!? Back in the days of updatable microcode rom (or today in the PII/III)
there was still a difference.

Though I have to admit that hardwired control units usually allow a higher clock rate.

> may well be pipelining of some sort inside the Z80, but it's not so
> obvious because of the less clear relationship between clock cycles and
> bus transactions on the Z80. Z80 machine cycles are more like 6502 clock
> cycles. I guess the Z80 doesn't make use of internal time constants to
> generate bus signals, whereas the 6502 does. The Z80 has a much faster
> running clock so that it can spend several clock cycles (T-states) on each
> bus transaction.

One reason for the high clock rate of the Z80 is the integrated DRAM controller.
The Clock has to be higher than the actual memory cycle clock since each RAM access requires several phases.
The 6502 does not interface its DRAMS directly and thus the help of a higher external clock signal is required for correct DRAM timing. You might compare this to the Z80 clock.