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| From: Richard Atkinson
Date: 2000-08-09
Subject: Re: Relative addressing
|
On Wed, 9 Aug 2000, Marko Mäkelä wrote:
> No, it's actually in the 5th cycle, while fetching the next opcode (which
> will not be thrown away, as the branch is not taken). This is the idea
> the 6502 designers have of pipelining. This also partially explains why
> the 6502 requires much less cycles per instruction than e.g. the Z80.
Not really; the Z80 is micro-coded, whereas the 6502 is hard-wired. There may well be pipelining of some sort inside the Z80, but it's not so obvious because of the less clear relationship between clock cycles and bus transactions on the Z80. Z80 machine cycles are more like 6502 clock cycles. I guess the Z80 doesn't make use of internal time constants to generate bus signals, whereas the 6502 does. The Z80 has a much faster running clock so that it can spend several clock cycles (T-states) on each bus transaction.
Richard
--
Richard Atkinson Software Engineer Tenison Technology EDA Ltd http://www.tenisontech.com/
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