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From: Marko_Mäkelä
Date: 2000-08-09
Subject: Re: Relative addressing

On Wed, 9 Aug 2000, Zsolt Prievara wrote:

> In the example in the 4th cycle the CPU executes the comparison of the
> "bcs". Am I right?

No, it's actually in the 5th cycle, while fetching the next opcode (which will not be thrown away, as the branch is not taken). This is the idea the 6502 designers have of pipelining. This also partially explains why the 6502 requires much less cycles per instruction than e.g. the Z80.

Technically, it would be possible to perform the comparison in the 2nd cycle, but I guess it would have complicated the circuit. The processor always starts the instruction execution in the 3rd cycle (which may be interleaved with the opcode fetch of the following instruction). I think instruction opcodes are decoded in the 2nd cycle.

Marko