Posted By
bubis
on 2019-10-31
12:51:25
|  Re: TED Rastertiming specs
Hi Exim,
Maybe this is what you saw, although there is no info on $FF1E in there: https://www.dropbox.com/s/n96a8z4bp87aaof/DFLI3.xlsx?dl=0
I posted this in this topic.
I have a XLS that is simmilar to whar you explained but that is unfinished and not all the info in it is 100% accurate, some of it is only guessing.
I can add some info on the "Name" row in the XLS above, but treat it with some skepticism please. 
There are 114 cycles in every rasterline, think about it as 57 pairs of cycles. The TED drives which cycle can be used by the CPU to run code and it can "steal" cycles even when we are in double clock mode. Let's assume we are in double clock mode.
DRAM1-DRAM5 is five cycles what the TED uses in every rasterline for DRAM refresh when $FF1E in 0x96-0xA8. This is why you can only count 109 cycles even on the border. This happens almost at the right edge of the visible screen. Run a "inc $ff19; jmp *-3" to see it.
DC01-DC16 are 16 double clock cycles when $FF1E is in 0xAA-0xC8. This starts a bit before the rigth border ends and mostly in the invisible area.
The rest only applies when the raster line is in 0-203 and the window is enabled.
SC is when the TED switches to single clock, it happens when $FF1E is in $0xCA-0xCC.
GR1-GR3 is when the CPU needs to stop executing any instuctions before DMA happens (badlines). This happens somewhere around the left border of the visible screen.
DMA happens when $FF1E is in 0xDA-0xE2 and 0x00-0x94. Both cycles are used by the TED when DMA happens. DMA start before the window opens and stops before the window closes.
Check here for info on DMA lines (badlines).
I didn't have too much time for this, sorry. I hope it will be useful.
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