Posted By
Litwr
on 2017-02-18
09:25:56
|  DRAM regeneration at C+4/16
Is this process known exactly? TED uses 5 memory accesses each raster line to regenerate DRAM. So TED uses 312*5=1560 accesses each screen with PAL computers and 260*5=1300 accesses with NTSC. These TED accesses are visible with HNY2013 demo, they are wider *dots*. Are addresses of these accesses known? There is a freeze mode which disables TED and therefore stops DRAM regeneration...
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Posted By
gerliczer
on 2017-02-18
09:38:21
| Re: DRAM regeneration at C+4/16
AFAIK: it reads continuously the $FF page ($FFXX), and no, it does not turn off DRAM refresh.
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Posted By
Litwr
on 2017-02-19
01:11:13
| Re: DRAM regeneration at C+4/16
Thank you very much.  This proves that reading one page is enough for DRAM regeneration. I checked TED documentation about freeze bit. It claims that TED stops to increase counters, is forced to single clock and refreshes DRAM. So TED refreshes DRAM on every cycle in the freeze mode, doesn't it?
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Posted By
gerliczer
on 2017-02-19
01:36:45
| Re: DRAM regeneration at C+4/16
You're welcome. The number of refresh reads necessary depends on actual DRAM organisation. AFAIK, 4164 requires 7 bit refresh scheme (maybe $FF80-$FFFF), however 41256 or 4464 requires 8 bit refresh (and 44256, imagine this, requires 9 bits). How actually that specific TED mode works is nowhere written in detail, or at the least I never met any such description. You should attach a logic analyser and check how it exactly works. Or take a look at the plus4emu sources. Maybe IstvanV made proper measurements to base the emulated TED behaviour on.
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Posted By
Gaia
on 2017-02-19
04:46:04
| Re: DRAM regeneration at C+4/16
Actually:
click me
Not sure if this fully answers your question though
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Posted By
siz
on 2017-02-19
07:38:35
| Re: DRAM regeneration at C+4/16
As it can be seen from Crown's post linked by Gaia TED has an 8 bit DRAM refresh. That's why you can replace the RAM chips in a plus/4 to 41256s easily. (they are replaced in mine plus/4 too)
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Posted By
MMS
on 2017-02-19
07:38:59
 | Re: DRAM regeneration at C+4/16
would be nice to switch to SRAM, and switch off refresh, thus making the full machine faster, same speed as on the borders.
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Posted By
Litwr
on 2017-02-19
08:28:43
| Re: DRAM regeneration at C+4/16
It is an interesting opportunity to disable DRAM refreshing and to get 5-7% speed gain. This requires to write self refreshing programs or using a special interrupt routine. However it is impossible with TED. This feature presents in the world of Dragons or CoCo though.
IMHO 5 ticks per a raster line are too much. Even one tick per a line is enough. However I do not completely understand that TED may read ROM during refreshing accesses. This may cause DRAM content loss for longtime ROM routine.
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Posted By
MMS
on 2017-02-19
15:06:22
| Re: DRAM regeneration at C+4/16
They are on the same address, right? Maybe just reading the ROM they activate the DRAM RAS /CAS lines too. But this idea complete BS too. 😀
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Posted By
MMS
on 2017-02-19
18:36:41
| Re: DRAM regeneration at C+4/16
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Posted By
MMS
on 2017-02-19
18:36:28
| Re: DRAM regeneration at C+4/16
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Posted By
JamesD
on 2017-02-19
17:40:10
| Re: DRAM regeneration at C+4/16
That won't activate the chip select.
*edit*
Writing to ROM would work.
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