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| | Previous Messages | Posted By
MMS
on 2020-02-17
05:21:20
 |  Re: TED Rastertiming specs
yes, I know. Sorry for the missing documentation (in the name of Commodore Business Machines).
Yepp,I found somthing at Zimmers. From Bil Herd, and has a lot of timing diagrams:
http://www.zimmers.net/anonftp/pub/cbm/schematics/computers/plus4/264_Hardware_Spec.pdf
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Posted By
Exin
on 2019-12-03
07:08:03
| Re: TED Rastertiming specs
Thanks, but I know that page. But the one I was looking for had a screen layout. 
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Posted By
MMS
on 2019-12-03
11:50:22
| Re: TED Rastertiming specs
Also there is a good article about the TED from TLC (Levente) in C= Hacking News
While it starts as a basic introduction of TED (and similaritis to VIC-II), it gives some insight about the timings too
(Levente's article is at the end of the mag)
http://www.ffd2.com/fridge/chacking/c=hacking12.txt
QUOTE
The TED IC is able to generate both PAL and NTSC compatible signals from
a single IC. Only the crystal need be changed to go from one standard to
the other. In PAL mode, there are 312 lines hown, while NTSC only has 262
lines of display. The line synchronization is the same in either PAL or
NTSC mode. It's always 57 clock cycles per rasterline. The TED divides
the supplied crystal frequency by 20 for PAL display and by 16 for NTSC.
For the serious video programmer, raster interrupts are implemented as on the
VIC-II. However, the 0 line of the register corresponds to the first line
of the character screen area, not the top of the border. In addition, the
current raster line can be read from TED registers. you can modify the
counter as well. Doing so will most likely affect the screen display. As
a bonus, the horizontal location of the raster can be read and modified in
the same way. Unfortunately, these registers provide the basis for most
effects, as the TED can't handle sprites.
@(A): Running The Show
As earlier mentioned, the TED IC does more than produce graphics. One of
its tasks involves generating the clock signal for the 7501/8501
microprocessor. The clock is not constant, as it switches from from
885 kHz and twice that speed, 1.773 Mhz. The speed depends on TED's current
task. It generates the slower clock signal when refreshing DRAM or fetching
data for the video screen. Otherwise, the high clock signal is generated.
The user can disable fast clock generation via a register. The end result
is a machine that operates at approximately 1 MHz, as the CPU runs in slow
mode while the screen is displayed, and operates in fast mode when the
TED starts drawing the top and bottom borders.
UNQUTE
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Posted By
Exin
on 2019-11-01
05:05:28
| Re: TED Rastertiming specs
((READING INTENSIFIES))
Thanks Bubis, I will try and verify this in Yape. I already knew that the DRAM Refresh is somewhere at the right side and always wondered if this DRAM refresh is like a 'soft refresh' like on Atari XL where you still have some cycles left, or if it is a 'hard refresh' where the area is exactly 5ms on screen, where the CPU is completely blocked and therefore 'thinner'.
The Refresh on Atari is in the left side/middle the screen, but very wide. Almost a hand wide when placed on the screen. However, Graph2Font basically took the burden off me of cycle counting because it was made for this exact purpose. 
I want to do something in the sideborder, other than just showing bitmap. Like, changing colors, experiment with scrolling etc. and wanted to know how much time there is before and after the stretched area.
Thanks alot for this info, especially the contents of the raster counter registers! 
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Posted By
bubis
on 2019-10-31
12:51:25
| Re: TED Rastertiming specs
Hi Exim,
Maybe this is what you saw, although there is no info on $FF1E in there: https://www.dropbox.com/s/n96a8z4bp87aaof/DFLI3.xlsx?dl=0
I posted this in this topic.
I have a XLS that is simmilar to whar you explained but that is unfinished and not all the info in it is 100% accurate, some of it is only guessing.
I can add some info on the "Name" row in the XLS above, but treat it with some skepticism please.
There are 114 cycles in every rasterline, think about it as 57 pairs of cycles. The TED drives which cycle can be used by the CPU to run code and it can "steal" cycles even when we are in double clock mode. Let's assume we are in double clock mode.
DRAM1-DRAM5 is five cycles what the TED uses in every rasterline for DRAM refresh when $FF1E in 0x96-0xA8. This is why you can only count 109 cycles even on the border. This happens almost at the right edge of the visible screen. Run a "inc $ff19; jmp *-3" to see it.
DC01-DC16 are 16 double clock cycles when $FF1E is in 0xAA-0xC8. This starts a bit before the rigth border ends and mostly in the invisible area.
The rest only applies when the raster line is in 0-203 and the window is enabled.
SC is when the TED switches to single clock, it happens when $FF1E is in $0xCA-0xCC.
GR1-GR3 is when the CPU needs to stop executing any instuctions before DMA happens (badlines). This happens somewhere around the left border of the visible screen.
DMA happens when $FF1E is in 0xDA-0xE2 and 0x00-0x94. Both cycles are used by the TED when DMA happens. DMA start before the window opens and stops before the window closes.
Check here for info on DMA lines (badlines).
I didn't have too much time for this, sorry. I hope it will be useful.
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Posted By
Exin
on 2019-10-30
05:00:38
| Re: TED Rastertiming specs
MMS: The diagram looked very similar, except the pictures were more detailed. For example, different diagrams for PAL and NTSC.
gerliczer: It was a webpage, though, not a document.
I think I last saw it around 2015. Or am I going mad? I thought this was a cool page, I used it to experiment on some raster tricks and wanted to pick up on it again....
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Posted By
gerliczer
on 2019-10-30
03:40:44
| Re: TED Rastertiming specs
I don't remember any such document either. The the things come closest are the TED documentation (Plus 4 Technical Docs, pg. 34-35) linked by SVS above and the hardware sheet of his excellent Ultimate Map. These documents combined may produce the needed information.
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Posted By
MMS
on 2019-10-30
03:12:08
| Re: TED Rastertiming specs
Such a thing I saw only with C64, the VIC article from Christian Bauer (1996).
https://csdb.dk/release/?id=44685
It the past it was in discussion, that a big potion of that acticle can be easily converted to Plus/4 easily (due to big similarities in graphics modes), some other cannot (sprite). Some sections can be made just based on available C= and other documentations.
Certainly the raster timing, block diagrams, FLI stuff, border handling/tricks and special effect stuff need to be completely different. To the later ones very detailed TED knowledge is required, and high level of programming skills (maybe some trial and fail method to be used).
Some of them already well documented in the Effects programming section, like FLI, so could be 'almost" copy/paste from there:
plus4encyclopedia/500027
plus4encyclopedia/500152
On this scene I think half dozen of active people owns the detailed knowledge of exact raster timing, including the ppl who wrote those nice emulators. I think most of them prefer writing programs instead of writing documentation
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Posted By
Exin
on 2019-10-30
02:33:58
| Re: TED Rastertiming specs
Unfortunately that's not it. That's just hardware schematics.
It was a programming page that had pictures on how many CPU cycles are used/free in every screenmode in which area of the screen (Border, retrace, etc)....
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Posted By
Exin
on 2019-10-29
06:52:30
| TED Rastertiming specs
Hi!
Years ago, I saw a webpage with the rastertimings explained in high detail. I cannot find it anymore...
It was with pictures where which value of which raster register (FF1C - FF1F) is.
Does anyone know where it is?
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