Posted By
GeorgeHug
on 2021-11-26
11:22:43
|  Question about the 8551 ACIA
I was looking at this site for information about code for servicing the ACIA:
http://csbruce.com/cbm/ftp/reference/swiftlink.txt
It's about the SwiftLink for the C64, but contains the following information about bit 7 of the Status register of the 6551 used in the SwiftLink:
"Some programmers have reported problems with using bit #7 to verify ACIA
interrupts. At 9600 bps and higher, the ACIA generates interrupts properly,
and bits #3--#6 (described below) are set to reflect the cause of the
interrupt, as they should. But, bit #7 is not consistently set. At speeds
under 9600 bps, bit #7 seems to work as designed. To avoid any difficulties,
the sample code below ignores bit #7 and tests the four interrupt source bits
directly."
Does anyone have any information about whether this problem also affects the 8551 used in the Plus/4? At high speed you would have occasional dropped characters. A received byte would not be read from the Data register, and would be overwritten by the next character coming in. The Plus.4 IRQ routine skips over all ACIA processing if bit 7 is cleared since it assumes the ACIA is not the source of the interrupt.
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