Posted By
gerliczer
on 2016-09-22
03:26:33
|  Re: What would I do differently in the Plus/4
@Litwr: I think you are wrong. I don't know anything about the ARM processors, but Z80 works completely different than 6502. The 6502 does a memory access in every clock cycle, the Z80 doesn't.
Z80 has so called T-cycles and M-cycles. T-cycles are the actual clock signal, therefore if a Z80 runs at 4 MHz then there are four million T-cycles in every second. M-cycles are the memory access cycles. These are those instances when the Z80 turns to the memory to fetch instructions and addresses, read or write data. There is a special output on the Z80 called M1 which signals when the processor fetches the next instruction. Also there's a special input like on the 6502s that signals to the processor that the memory operation is not finished so it should wait to complete the current instruction. The number of M-cycles is a fraction of the T-cycles. I don't know exactly how it works, but if my mind serves me well, there are at least 4 T-cycles between two M-cycles. So, the memory access frequency is quite similar in both kinds of systems. There's no such thing as z80 systems use RAM at 3.5-4 MHz.
Especially because memory of these systems simply does not have that necessary speed. I read in the datasheet of the NEC 41256 DRAM that even the so called 100 ns speed grade memory ICs have a cycle time of 220 ns. The 100 ns is the time under which the read or write operation is executed. However, the IC needs an additional 120 ns to prepare for the next memory access. That means that even with these quite fast RAMs the system may access the memory at ~4.5 MHz at best. Can you imagine what happens in systems that has 150, 200 or even 300 ns RAMs? Furthermore, do you think that it was only by mistake that these systems not used the best memory available? Or did it have something to do with price?
An example for the memory access situation. The Enterprise, a nice Z80 based machine, has dedicated video RAM. The video controller runs its memory bus slightly under 900 kHz because of raster line timing reasons, and does 3 memory accesses in every clock cycle. Two is used by the video chip, the third is available for the CPU, which runs at 4 MHz. The memory accesses are obviously unaligned no matter what is done, therefore the video controller is capable of stretching the clock cycle of the processor to synchronize its read or write with the video memory bus clock. Another interesting part of the system is that the main memory system has a control flag, which when turned on adds one clock cycle delay to the memory accesses. The documentation says that it is there for machines built with slow, I think it explicitly says 300 ns or slower, RAM.
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