Posted By
TLC
on 2007-02-08
11:36:18
|  Re: Plus/4 Expansion port...
I cannot inspect the IP addresses of people visiting this forum <grin> so, may I ask you who you are? 
As to how write cycles happen during different opcodes, it can be summarized pretty shortly:
-- Opcodes that execute a single write cycle (e.g. all write operands, like sta, stx, sty, the opcodes putting a byte onto the stack like pha and php + the illegal opcode variants of these all) all do this at the very last cycle of the opcode. (E.g. the next CPU read cycle after a single CPU write cycle is predictably an opcode fetch of the next instruction).
-- The majority of the opcodes that execute two consecutive write cycles are read-modify-write instructions (e.g. inc, dec, rol, ror, asl, lsr (except the implied addressing versions of these latter four) and their illegal variants. These actually write the original value back to the memory address before they'd write the modified value (this won't be functionally neccessary, it's actually a phenomenon of the simple design of the 65xx). This happens, similarly to the group above, at the last cycles of the operand. The problem is, that there's one more, 2-consecutive-write-cycle opcode, the JSR, which is different. (The JSR pushes the 2 bytes of the current PC value onto the stack _before_ finally reading the high byte of the target address).
-- There's only one case when 3 consecutive write cycles are executed: the interrupt mechanism, including the execution of a BRK (push PCH, PCL and SR). This also won't happen at the last cycles of the "operand" ($fffe and $ffff are fetched after this).
You can read more about these (for example) in the 64doc article by Marko Mäkelä and John West (http://www.6502.org/users/andre/petindex/local/64doc.txt).
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